Selecting an ESD Diode for a High-Impedance Sensor Input: Leakage Comes First

Author: ASIM Technical Team | Published: 2026-09-12

On a high-impedance sensor input, the off-state behavior of an ESD diode can set the measurement error before any electrostatic event occurs. Capacitance still matters, and clamp performance still matters, but leakage current must be converted into input error at the circuit's operating temperature. A room-temperature typical value is not enough for approval.

Turn leakage into the unit the sensor cares about

For a first screening calculation, the voltage error created by diode leakage is:

ΔV ≈ IR × Rsource

IR is the leakage component that flows through the effective source impedance, and Rsource is the impedance seen at the protected node. The equation is intentionally simple. It does not include input-bias current, surface contamination, connector leakage, PCB insulation, or amplifier offset, but it shows whether the ESD part can fit the error budget at all.

Consider three arithmetic examples, not product claims:

The same diode leakage can be harmless on one interface and dominant on another. That is why “low leakage” without a voltage, temperature, and maximum limit is not an engineering specification.

Build the error budget before searching a catalog

Start with the allowable error at the protected node. Subtract the contributions already assigned to the sensor, bias network, amplifier input, ADC, connector, and PCB. The remainder is the budget available to the protection branch.

For example, if the remaining node-error budget is 5 mV and the effective source impedance is 500 kΩ, the leakage allocation is 10 nA. This is a calculation from the assumed budget, not a statement that a particular ESD diode has 10 nA leakage. It tells the designer what maximum value must be found and verified.

Use worst-case values for the decision. A typical value describes a central result under one condition. It does not bound production spread. If the datasheet provides only a room-temperature typical leakage and the product operates hot, request maximum data at the relevant reverse voltage and temperature or measure enough samples to define the risk.

Temperature can reverse a room-temperature decision

Reverse leakage in semiconductor protection devices generally rises with junction temperature. The exact relationship depends on device design, voltage, and manufacturing distribution. It should be taken from a controlled datasheet curve or a supplier report rather than assumed from a rule of thumb.

A useful bench sequence is:

1. measure the unprotected channel or a low-leakage control path;

2. install the candidate protection device and measure at room temperature;

3. repeat at the lowest and highest product temperatures after stabilization;

4. measure across the full normal input-voltage range;

5. repeat after the required ESD stress to detect permanent leakage shift.

Record board cleanliness and humidity if the current is in the nanoampere range. Flux residue and surface moisture can create a parallel leakage path that is larger than the device current. Guarding, fixture insulation, cable choice, and instrument input current also become part of the measurement.

Capacitance and leakage solve different problems

Low-capacitance ESD diodes are often chosen for high-speed links because junction capacitance can close an eye diagram or add insertion loss. A sensor input may have low bandwidth but high source impedance. In that case, a part with attractive capacitance can still be unsuitable if its leakage consumes the error budget.

Keep the two checks separate:

• capacitance is evaluated against bandwidth, settling time, filter response, and stability;

• leakage is evaluated against source impedance, DC accuracy, temperature, and recovery after stress.

For switched or sampled sensors, capacitance may also affect acquisition time. The protection capacitance, amplifier input capacitance, PCB capacitance, and source resistance form a settling network. Both leakage and capacitance can therefore matter, but they appear in different calculations.

Working voltage must cover every normal state

The diode's reverse working voltage should be checked against more than the nominal sensor output. Include power sequencing, calibration states, common-mode range, bias faults, cable hot-plug behavior, and any test mode that can hold the node near a rail.

Operating too close to the protection knee can increase leakage and nonlinearity. Choosing a much higher working voltage may reduce conduction during normal operation, but it can also increase the residual voltage during an ESD event. The correct choice sits between two limits: stay sufficiently off in every normal state and clamp low enough for the protected input.

Verify clamp behavior at the protected pin

Leakage approval does not complete the ESD design. Measure the transient at the sensitive pin or a representative test point instead of limiting the measurement to the protection-diode terminals. The observed IC-side voltage includes the device clamp plus layout effects.

Place the diversion path close to the entry point, keep the branch short, and provide a low-inductance return that does not share unnecessary impedance with the sensor reference. On a small signal, ground movement can look like an input event even when the signal conductor itself is well clamped.

The test plan should specify discharge location, polarity, event count, operating state, and failure criterion. Monitor sensor output, ADC code, amplifier recovery, supply rail, and any latch or reset indication. A channel that returns slowly after a pulse may be functionally unacceptable even if no component is damaged.

Use a sample matrix that exposes variation

One hand-picked part cannot establish production behavior. A practical comparison includes multiple samples from multiple lots, especially when the leakage allocation is close to the datasheet limit. Keep the candidate code hidden from the operator when possible and use the same cleaned board or a controlled fixture.

Suggested result fields are:

• sample and lot identification;

• reverse voltage and polarity;

• stabilized temperature;

• initial leakage and channel offset;

• post-ESD leakage and recovery time;

• measured IC-side residual voltage;

• pass or fail against the predeclared circuit limit.

Do not average away a failing tail sample. For a limit-based design, the maximum relevant result often drives the decision.

ASIM's ESD diode manufacturer page can be used to locate protection-device information. Final selection for a high-impedance channel should be based on maximum leakage under the real bias and temperature conditions, followed by assembled-board ESD verification.

A decision order that prevents rework

Define normal voltage first. Convert the measurement error budget into an allowable leakage next. Then check maximum leakage across temperature, evaluate capacitance and settling, and screen the clamp voltage against the input's absolute limit. Finish with temperature and ESD tests on the intended board.

This order prevents a common failure: selecting by a low capacitance headline, finishing the layout, and discovering later that temperature-dependent leakage shifts the sensor reading.

High-Impedance Sensor ESD FAQ

Is typical room-temperature leakage sufficient for selection?

No. A limit-based design needs a maximum value at the applicable voltage and temperature, or project test data that establishes the range.

Should the lowest-leakage diode always be selected?

No. It must also remain off during normal states, provide suitable capacitance and transient clamping, fit the layout, and survive the required stress.

Why measure again after ESD stress?

A device can retain basic avalanche function while its off-state leakage has shifted. High-impedance channels may reveal that change as a persistent measurement offset.