ESD Diode Failure Analysis: Surge Tolerance and Short Circuit Risk-ASIM

I. Core Viewpoints

The failure of ESD diodes is an inevitable result of the combination of energy overload, insufficient design margin and harsh operating environment. Surge tolerance is not a static parameter but a functional characteristic that varies dynamically with pulse width, repetition frequency, ambient temperature and PCB layout. Short-circuit failures account for over 60% of the total failures of ESD diodes. The core mechanism is that transient energy forms a hot spot in a local area of the PN junction. When the junction temperature exceeds the melting point of the silicon material, the lattice structure melts and solidifies into a permanent conductive channel. This failure mode is covert and destructive - after failure, the device is in a low-resistance state, with continuous leakage current reaching tens of milliamperes, causing the PCB copper foil to overheat and carbonize, adjacent components to be damaged as a result, and even posing a fire risk.

Ii. Main Failure Modes and Mechanisms

Short-circuit failure

When the surge current exceeds 1.5 times the rated peak pulse current (IPP) of the device, the heat generated in the avalanche breakdown region cannot be dissipated in time through the package. Anatomical analysis revealed that the surface of the failed chip presented molten pits with diameters ranging from 0.1 to 0.5mm, and under the metallographic microscope, traces of metallization and burning after the reconstruction of the silicon lattice could be seen. Data from Assem's Failure Analysis Laboratory shows that 85% of short-circuit failure cases are caused by insufficient design margin of IPP, while only 10% are due to excessive thermal resistance of the package.

Open-circuit failure

The melting of the bonding wire is the main cause of open-circuit failure. When the surge current rise rate di/dt exceeds 10⁹ A/s, the bonding alloy wire breaks within 1 to 10ns due to the electromigration effect. This failure accounts for approximately 25% and is highly concealed - the TVS loses its protective function but the circuit can still operate until the next surge event directly damages the subsequent IC. This kind of failure occurred in the 6kV surge test of the ASIM SMAJ100CA model. The fundamental reason was that the excessive parasitic inductance led to current concentration.

Parameter drift failure

Long-term high-temperature reverse bias (HTRB) or repeated surge impacts can cause lattice damage to silicon materials, with the breakdown voltage VBR dropping by 5% to 15% and the leakage current IR increasing to the microampere level. This type of failure accounts for 15% and can be identified in advance through regular parameter testing. The Assem SMB15J series, at a rated power of 1500W, has a VBR offset of less than 3% after 1000 8/20μs pulses. If this threshold is exceeded, it is determined to be a potential failure.

Iii. Analysis of Key Influencing Factors of Surge Tolerance and Short Circuit Risk

The peak pulse power Pppm is matched with the pulse width

Narrow pulses (100ns ESD) can fully utilize Pppm, while wide pulses (1ms lightning strike) need to be derated to below 50%. The Assem SM8566J series is marked with 6600W (10/1000μs), but in reality, when withstanding 8/20μs pulses, its capacity can exceed 8000W. If the 6600W value is wrongly applied to the 1ms pulse design, the actual tolerance capacity will only be 3300W, and the short-circuit risk will increase by 300%.

IPP rated values and current concentration effects

IPP is a core parameter for surge tolerance. The Assem ESD5M020TR-5L model has an IPP of 5A (8/20μs) and can withstand ±30kV contact discharge. However, actual measurements show that when the actual surge current reaches 7.5A, the short-circuit probability jumps from 0.1% to 15%. When multiple TVS devices are connected in parallel, due to the discretization of device parameters, the current distribution is uneven, and the local current may exceed the IPP by more than 30%. Therefore, an additional 10% derating is required for use. The Assem SMB15J series reduces the parallel derating requirement to 5% through ±5% breakdown voltage accuracy control.

Encapsulation thermal resistance and heat dissipation path

The thermal resistance of SOD-123 package is approximately 62 ° C /W, that of SMA package is about 40 ° C /W, and that of SMC package with heat dissipation pads can be reduced to 15 ° C /W. The Assem failure case shows that the junction temperature of the same chip in SOD-123 package reaches 185℃ at an average power of 5W, while in SMC package it is only 95℃. When the copper area of a PCB is less than 10mm², the thermal resistance increases by more than 50%, and the short-circuit failure time is shortened from 1000 hours to 200 hours.

Ambient temperature and temperature derating

For every 10℃ increase in junction temperature above the 25℃ benchmark, the Pppm capacity decreases by 5% to 8%. The Pppm of the AsSEM SMB15J series drops from 1500W to 900W at 125℃. For automotive electronic applications, the 5b waveform (202V) of ISO 16750-2 must be met. If the derating at an ambient temperature of 125 ° C is not taken into account, the claimed 1500W device actually only bears 900W, increasing the short-circuit risk by 67%.

Parasitic parameters of PCB layout

When the TVS is more than 20mm away from the protected IC, the parasitic inductance can reach 15 to 30nH, generating an additional voltage drop of 15 to 30V under a surge current of 100A/ns, which reduces the actual clamping effect of the TVS by 40%. In the case of the Asem 5G base station, the SMAJ100CA model caused the residual voltage to rise from 28V to 42V due to a 30mm trace length, resulting in a breakdown and short circuit of the back-end chip. When the impedance of the grounding loop exceeds 5mΩ, the surge current cannot be effectively discharged, and heat accumulates inside the TVS.

The number of repeated surges and lifetime exhaustion

TVS has a clear lifetime model. The Assem ESD0524V015T model can withstand 1000 pulses under ±30kV contact discharge, but after more than 2000 pulses, the VBR drops by more than 10%, and the leakage current increases to 5μA, entering a pre-failure state. Under the frequent ESD testing environment on industrial production lines (100 times a day), the lifespan of devices has been shortened from the theoretical 10 years to 3 months.

Iv. Preventive and Improvement Measures

Margin guarantee in the design stage

Power margin: Actual surge power ≤ nominal Pppm × 70% (Class A) or 80% (Class B)

Current margin: Actual IP ≤ nominal IPP × 1.5 times

Voltage margin: The clamping voltage VC ≤ 80% of the withstand voltage of the protected IC

Temperature margin: The Pppm is still greater than the actual power demand after derating at the highest ambient temperature

Practical Application of Asem Model Selection

Consumer electronics USB port: ESD5M020TR-5L, IPP=5A, Pppm=200W, meeting ±30kV ESD and 2kV surge requirements

Industrial 24V power supply: SMB15J33A, Pppm=1500W, IPP=75A, 8/20μs pulse withstand over 1000 times

New energy vehicle CAN bus: SM8566J33A, Pppm=6600W, IPP=270A, passed ISO 16750-2 5b waveform test

5G base station power supply: ASD12N series, Pppm=5000W, response time 0.5ns, junction capacitance 3pF

Rigid constraints on PCB layout

1. Distance control: The TVS distance from the interface or IC should be ≤ 10mm. If it exceeds 20mm, the failure probability increases by 40%

2. Grounding design: The GND pin should be directly connected to the main ground plane. Long and thin serpentine wires are prohibited. There should be no less than 4 independent vias with an impedance of less than 5mΩ

3. Routing specification: The routing width between TVS and the protected IC should be no less than 0.5mm. It is strictly prohibited to lead out branches in the protection path

4. Thermal design: The copper area of the TVS pad should be no less than 10mm², and the distance between adjacent components should be no less than 5mm to avoid thermal coupling

Hierarchical protection architecture

The first stage: High-power TVS (such as Assem P600 series) is adopted to withstand the main energy, with Pppm≥5000W

The second level: Use low-capacitance ESD diodes (such as ESD0322) for fine clamping, with an IPP of ≥5A

Level 3: Add self-resetting fuses to form a fail-safe mechanism. When a TVS short circuit occurs, the fuse blows to prevent the system from crashing

Test verification closed loop

TLP test: To evaluate the stability of dynamic resistance, Assem requires that the Rdyn change rate be less than 10%

HBM/CDM test: Verify process reliability. ESD5M020TR-5L passed the HBM 30kV test

High-temperature reverse bias: At 125 ° C /VRWM for 1000 hours, the leakage current increment is less than 0.1μA

Repeated surges: VBR offset<5% after 1000 8/20μs pulses

Supply chain quality management

Asem offers device authenticity verification services. Through X-ray comparison, parameter distribution analysis, and FTIR spectroscopy detection of packaging materials, it can identify counterfeit and substandard products. Batch tracking data for 2024 shows that the short-circuit failure rate of counterfeit devices is 8.3 times that of original factory devices. It is recommended to purchase from an authorized agent and request the provision of batch test reports.

五、Conclusion

The surge tolerance and short-circuit risk of ESD diodes are two sides of the same coin in engineering trade-offs. Short-circuit failure is not an accidental event, but a predictable result of the combined effect of four major factors: insufficient IPP margin, heat dissipation failure, layout mismatch and life exhaustion. The over 2,000 cases accumulated in the Asem Failure Analysis database show that 90% of short-circuit failures can be completely avoided through power derating (≥30%) in the design stage, PCB layout optimization (distance ≤10mm, copper laying ≥10mm²), and correct model selection (IPP≥1.5 times the actual current).

The core difference between power protection and signal protection lies in that the former deals with joule-level energy, focusing on Pppm, IPP and thermal resistance. The latter deals with picojoule-level energy, focusing on Cj and insertion loss. Engineers must establish a parameter database based on real models (such as Assem SMB15J series 1500W, SM8566J series 6600W, ESD5M020TR-5L 5A), and combine TLP testing, high-temperature reverse offset verification and repeated surge life assessment to form a complete protection chain from selection, layout to testing. Only by elevating derating design from an empirical rule to a quantitative engineering criterion can true high reliability be achieved under the threat of static electricity and surges.

About Assem Electronics

Shenzhen ASIM Electronics Co., LTD. (ASIM) was established in 2013 and is a national high-tech enterprise, specializing in the field of circuit protection components. An investment of 5 million yuan was made to establish an EMC experimental center in Shenzhen, providing services such as failure analysis, component selection, PCB layout optimization and surge environment measurement. The TVS product line covers SOD-123FL, SMA, SMB, SMC, P600, and DO-218AB packages, with peak power ranging from 200W to 6600W. It has passed the AEC-Q101 automotive-grade certification and UL safety certification, providing customers with full-process technical support from design to mass production.