How to Evaluate ESD Diode Capacitance: Test Frequency, Bias, Differential Loading, and S-Parameters

An ESD diode capacitance value is comparable only when the complete part number, test frequency, DC bias, port configuration, temperature, and statistical limit are known. A small typical Cj value is useful for screening, but it does not by itself establish insertion loss, return loss, eye margin, or suitability for a named high-speed interface. For GHz-range links, review S21, S11, the PCB implementation, and target-board measurements as separate evidence.

A capacitance number needs a measurement definition

Data sheets may use Cj, Cd, or Ct for values that are casually translated as junction capacitance. The labels are not always interchangeable. One document may specify a single diode between two terminals; another may specify one I/O pin to a shared rail; an array document may use a multiport configuration. The schematic and test conditions determine what the number represents.

Record the following fields before comparing candidates:

Nexperia's ESD design handbook describes 1 MHz and zero bias as a commonly used capacitance measurement condition and also explains that reverse bias changes the measured capacitance. That is useful context, not permission to assume that every vendor used the same setup. The current data sheet for the exact part remains the controlling source.

Bias dependence belongs in the same row as Cj

A reverse-biased junction is not a fixed capacitor. As the bias changes, the depletion region changes and so does the capacitance. If a signal line operates around a DC common-mode voltage, a zero-bias typical value may not describe the operating region.

A practical review follows four steps:

1. Write the minimum, nominal, and maximum line-to-ground voltage for every relevant power state.

2. Check whether the data sheet provides a capacitance-versus-bias curve and identify the frequency and port used for that curve.

3. If only one typical point is available, use it to remove clearly unsuitable parts, not as a guaranteed maximum.

4. On analog or high-impedance nodes, review reverse leakage with its voltage and temperature conditions as well as capacitance.

Do not borrow a bias curve from a similar-looking device. Process, junction area, protection topology, package, and fixture can all change the result. Missing data should remain a qualification question rather than being filled with an estimate from another part.

Single-ended Cj does not define a differential channel

A differential channel is affected by more than the capacitance from each conductor to ground. Pair symmetry, channel-to-channel coupling, shared rails, package inductance, pad geometry, and branch length can all contribute to mode conversion, reflection, and loss. An array advertised with a per-channel value has not automatically described the complete network seen by the differential pair.

Before translating a single-ended number into a differential model, verify:

• whether the capacitance is defined from one I/O to a common node or between two ports;

• the array topology and the connection of any shared pin;

• the Touchstone port map and reference impedance;

• whether the two signal conductors use geometrically matched PCB branches;

• whether evaluation-board pads or fixture effects remain in the model;

• the de-embedding plane and frequency range.

Without those definitions, multiplying or dividing the data-sheet number does not create a valid differential result. Obtain the port model first, then perform the appropriate conversion or simulation.

Why S21 and S11 matter at high frequencies

Cj reduces the device to one element. That approximation can be useful at an early screening stage, but it omits package inductance, resistance, pads, and resonance. At sufficiently high frequency, two devices with similar quoted capacitance can have different insertion-loss and return-loss behavior.

Nexperia's USB4 technical note states that ESD protection for GHz-range links should be evaluated with S-parameters, particularly S21 for added insertion loss and S11 for return loss. The note also explains that measurement equipment commonly uses 50-ohm single-ended ports, while the target USB4 differential impedance is not identical to the test-system impedance. The model therefore needs to be placed in the real channel context.

An S-parameter file is not self-validating. Confirm the file name, part suffix, package, port mapping, and measurement board before using it. A model for one package should not be attached to another package simply because the family name is similar.

Reference capacitance tables are not universal limits

ROHM's December 2023 application note, Selection Method and Usage of TVS Diodes, includes reference capacitance values for several interfaces. The document explicitly labels the values as reference guidance and requires confirmation in the actual equipment. Preserving that limitation matters.

An interface name does not fully specify channel loss. Protocol generation, negotiated data rate, trace length, material, connector, vias, equalization, and receiver margin can differ between two products using the same connector. Removing the “reference” and “verify in the actual equipment” language would turn manufacturer guidance into a universal threshold that the source does not support.

Use such tables to understand why capacitance and parasitics become more restrictive as link bandwidth rises. Do not use them as a pass/fail substitute for the actual channel budget.

Keep data-sheet, model, and board conclusions separate

For a board comparison, keep the PCB revision, cable, lane mode, instrument bandwidth, fixture, probe location, and software settings fixed. An A/B/A sequence is useful: measure candidate A, replace it with candidate B, and then restore A. If the restored configuration does not reproduce the first result, rework or test drift may be larger than the part difference.

When an ASIM part can enter a public comparison

An internal ASIM product table can identify candidate parts, but a spreadsheet cell containing Cj is not a substitute for a controlled specification. ASIM Technical Team will place a part in a public comparison only after the current formal data sheet establishes the full orderable number, frequency, bias, port definition, typical or maximum status, package, and document revision.

A claim that a part supports USB4, HDMI, MIPI, or another high-speed interface requires additional evidence: a matching S-parameter file and target-board signal validation. Until those are available, the accurate status is “candidate pending model and board verification.”

Questions engineers commonly ask

Does lower Cj always mean better ESD protection?

No. Cj describes one aspect of normal-signal loading. Protection also depends on clamping behavior, dynamic resistance, current path, package and PCB inductance, and the protected IC's tolerance. Lower capacitance does not automatically establish lower insertion loss or a better system-level ESD result.

Can a typical Cj value be used when no maximum is published?

It can be used for preliminary screening. It should not be treated as a production maximum. Ask the manufacturer for a limit or distribution information and validate adequate margin on the target board.

Is a Touchstone file enough to release the design?

No. It represents a stated model and reference plane. The implemented land pattern, branch, connector, stack-up, and manufacturing variation remain outside that file and require board-level verification.

Data and primary sources

• Nexperia ESD Design Engineer's Guide — capacitance measurement conditions, bias dependence, and S-parameter concepts.

• Nexperia: Selecting ESD protection for USB4 data lines — the use of S21 and S11 for high-frequency evaluation.

• ROHM Application Note No. 66AN047C, Rev.001, December 2023 — reference capacitance guidance and target-equipment verification.