How to Build a TVS Diode Selection Checklist

A TVS diode selection checklist should turn an informal statement such as “this is a 24 V part” into a traceable voltage and energy review. Start by excluding devices that may conduct during normal operation. Then verify the residual voltage at the real surge condition. Only after those checks should package size, cost, and availability decide between candidates.

Many selection sheets fail because they stop at voltage class and peak pulse power. A row that says “24 V, 600 W, SMB” does not tell a reviewer which pulse waveform was used, what current corresponds to the listed clamp voltage, or whether the downstream IC can survive the voltage at its own pins.

What columns belong in the selection sheet?

The checklist should include the protected node as well as the TVS part number. A useful sheet contains these fields:

• highest continuous voltage at the TVS location, including supply tolerance, charging state, ripple, and allowed abnormal operation;
• device VRWM, minimum and maximum VBR, reverse leakage, and the conditions associated with each value;
• maximum VC, the corresponding IPP, pulse waveform, pulse width, and peak pulse power condition;
• unidirectional or bidirectional structure, package, land pattern, and intended return path;
• absolute maximum and functional voltage limits of the downstream IC, converter, MOSFET, or transceiver;
• ambient temperature, repeated-pulse interval, cable source impedance, and expected stress path;
• verification data from the board, including TVS-terminal voltage, protected-pin voltage, function, and post-test leakage.

The sheet should also distinguish maximum, minimum, typical, and measured values. A typical VBR copied beside a maximum clamp voltage looks complete, but it mixes different confidence levels.

Begin with the actual working voltage

Nominal voltage is rarely the right number. A 12 V rail can see charging voltage and load variation. A 24 V industrial input can see supply tolerance, long-cable effects, and switching transients. A signal line may be driven while the local board is unpowered. The first calculation therefore uses the highest sustained voltage the TVS can see at its physical location.

Use this review order:

1. Establish maximum continuous voltage and the cold operating condition. Select a VRWM that does not create unwanted conduction in normal use.
2. Check the VBR range and temperature behavior. Do not treat a 25°C typical value as a whole-temperature guarantee.
3. Read maximum VC at the expected surge current and the applicable waveform.
4. Add package, trace, via, and return-path overshoot to the voltage expected at the protected pin.
5. Check pulse energy, repetition, thermal conditions, and any sustained-fault current against the intended protection architecture.

If the clamp-side voltage has no margin at step three or four, moving to a larger pulse-power package may not fix the design. A shorter return path, upstream current limiting, or a different voltage class may be required.

What does a 24 V candidate comparison show?

The ASIM SMA04J24V, SMB06J24V, and SMC15J24V each have a 24 V VRWM and a VBR range of 26.7 to 29.5 V. All list a maximum VC of 38.9 V. Their associated IPP values are 10.3 A, 15.5 A, and 38.6 A respectively, and their packages and peak pulse power classes differ.

This is the kind of comparison that belongs in one selection sheet. It shows that one working-voltage class can contain devices with very different specified pulse capability. It does not mean that the three parts are interchangeable. The current values are tied to a test waveform, the package determines thermal and layout behavior, and 38.9 V must still be compared with the protected circuit plus PCB overshoot.

If the downstream IC can tolerate less than that voltage at its pins, the sheet should flag all three candidates. A low impedance source, a fast edge, or a long return path may create a protected-pin peak well above the voltage measured directly at the TVS.

Why package cannot be a late afterthought

SMA, SMB, and SMC describe package families; they are not automatic substitutes or fixed power levels. Pad size, copper area, via count, placement, and return topology change how pulse current spreads through the board.

Add a layout-status column to the selection sheet. It can be as simple as “at connector entry, two adjacent return vias” or “25 mm from connector, return path pending.” That note forces the electrical review to remain connected to the physical board.

Keep separate measurements for voltage across the TVS and voltage at the protected IC. A TVS can meet its own datasheet clamp condition while the IC pin sees a higher peak through trace inductance.

When should the spreadsheet stop deciding?

Move from paper comparison to controlled samples when any of these conditions apply:

• the datasheet lacks data at the required temperature or waveform;
• the path includes long cables, multiple boards, or complex chassis return routes;
• the stress is a long pulse, repeated pulse, or sustained overvoltage;
• the clamp margin to the downstream limit is small;
• the board already shows heating, increased leakage, resets, or intermittent failures.

The checklist is meant to make assumptions visible. It cannot replace a pulse waveform on the real assembly.

How should verification be recorded?

For each shortlisted part, document the sample identity, PCB revision, supply condition, pulse source, polarity, waveform, cable setup, probe method, and measurement locations. A single plot without its setup is difficult to reuse when another engineer reviews an alternate source months later.

Record peak voltages, post-test leakage, and product function. A TVS can remain non-shorted while its leakage or clamp behavior has drifted. That is particularly relevant when the design sees repeated stress rather than one qualification pulse.

Common questions

Is higher peak pulse power always better?

No. Peak pulse power is valid only under stated waveform, duration, and temperature conditions. It does not correct an unsuitable VRWM or a clamp voltage that exceeds the downstream limit.

Can VRWM be selected from nominal supply voltage?

No. Use the maximum continuous voltage, including tolerance and realistic operating states.

Is VC below an IC absolute maximum enough?

Not by itself. Add PCB overshoot and consider the functional margin. Some ICs reset or corrupt data before they suffer permanent damage.

Should board-test results appear in a selection sheet?

Yes. Include waveform files and both TVS-terminal and protected-pin voltage. That creates an audit trail for later BOM or layout changes.

A TVS selection is ready for release when the chosen model, its parameters, the physical return path, and the verification record all tell the same story. Leaving any one of those pieces out turns a candidate into an assumption.